When we talk about progress in microelectronics, for decades we have become accustomed to an almost automatic logic: a new processor means a smaller manufacturing process, more transistors on the same surface area, greater computing power, and lower energy consumption. We once spoke in micrometers, then in hundreds of nanometers, followed by 90, 45, 28, 14, 7, 5, and today 3 or even 2 nanometers.
For a long time, this development tracked Moore’s law closely enough that we almost forgot that it is not a law of physics, but an empirical regularity of an industry that managed, every few years, to reduce transistor dimensions and increase transistor density. But what happens when access to the next generation of lithography is no longer available?
Huawei and SMIC found themselves facing exactly that problem. Because of restricted access to EUV — Extreme Ultraviolet — lithography, the Chinese semiconductor industry cannot simply follow the same technological path as TSMC, Samsung, or Intel. DUV lithography can be pushed very far through multiple exposures, complex patterning, process optimization, and a great deal of engineering ingenuity, but cost and complexity rise very quickly.
Huawei therefore tried something else. If it is no longer easy enough to keep shrinking a chip across its surface, perhaps it is time to start building it upward.
When a Flat Surface Becomes a Limitation
A classic integrated circuit is, in simplified terms, a planar structure. Transistors are formed in a semiconductor layer, while above them there are multiple metal interconnect layers that connect billions of elements into a functional system.
In a modern processor, a significant portion of total delay no longer comes from the transistors alone. A signal has to travel through an extremely complex network of metal interconnects between registers, execution units, cache memories, controllers, and other functional blocks. Even if we build a very fast transistor, that speed is of limited use if the signal then has to travel a long distance to reach the part of the chip it needs.
Huawei calls its answer to this problem LogicFolding.
The Kirin 9050 Pro does not use only one active silicon layer, but two semiconductor layers placed one above the other and connected by very dense hybrid copper-to-copper links. Huawei associates this architecture with its broader concept of τ Scaling, according to which further progress should not be measured only by transistor dimensions, but also by the time required for signals and data to move through the system.
In other words, if we can no longer easily shorten the transistor, we can try to shorten the path between transistors.
A Processor Sandwich
The simplest way to imagine it is as a sandwich. Two “spread” silicon surfaces face one another, while an enormous number of extremely small copper connections sit between them. Instead of functional blocks communicating only horizontally through the metal interconnects of one large layer, they can also communicate vertically with a block located almost directly beneath them.
According to detailed analyses of the Kirin 9050 Pro, the upper semiconductor layer contains most of the compute logic, while the lower one contains large portions of the L1 and L2 cache, shared cache, I/O interfaces, and PLL circuits. The CPU, GPU, NPU (Neural Processing Unit), ISP (Image Signal Processor), and modem are not arranged so that one complete block is simply placed above another; individual functional structures are, in practice, vertically partitioned across the two silicon levels.
At this point, LogicFolding becomes much more than simply stacking two chips. A compute unit can have its corresponding memory block directly beneath it, so instead of relying on a long horizontal route to the cache, the signal can take a shortcut through the third dimension.
Fifty Million Small Shortcuts
It is precisely the density of these vertical connections that makes the architecture especially interesting. For this LogicFolding implementation, a hybrid-link pitch of about 1.5 micrometers and approximately 50 million interconnects between the two active semiconductor layers have been reported, with estimates suggesting that around 10 to 15 percent of them are used for signal transmission. Future generations are expected to reduce that pitch further and increase the total number of links beyond one hundred million.
This is a completely different category from the classic connection of separate chiplets through a package substrate.
And then there is another vertical infrastructure. Around 80,000 TSV — Through-Silicon Via — connections pass through the lower semiconductor layer and connect the chip to the package substrate. They carry power and signals to both silicon levels, including the upper compute layer. According to available analyses, the keep-out zones around these structures occupy roughly eight percent of the usable area of the lower layer.
If we continue with the road analogy, TSVs are vertical highways connecting the entire two-story city to the outside world, while the millions of Cu–Cu connections between the two layers are the dense local streets connecting its floors.
Why Is the “Hot” Part on Top?
The arrangement of the two layers is not accidental. The CPU, GPU, and NPU compute units generate more heat, so they are placed mainly on the upper layer, closer to the path through which heat is removed from the processor. Cache memory, PLL circuits, and part of the I/O logic are thermally less demanding and can occupy the lower layer, while also being better suited to a somewhat older manufacturing process.
According to currently available analyses, the compute layer is produced using SMIC’s N+3 process, while the lower layer uses N+2. It is important, however, to treat this process split as a conclusion based on independent analysis rather than as a simple official declaration of “5 nm + 7 nm.”
N+3 is often described as approaching some characteristics of the 5-nm class, but it is not accurate to simply declare it equivalent to a conventional 5-nm process of the type offered by manufacturers with access to EUV lithography.
And perhaps that is precisely the most important point. LogicFolding is not interesting because China somehow “made 5 nm without EUV.” It is interesting because it attempts to compensate for part of the manufacturing-process limitation by changing the architecture of the chip itself.
When a Shorter Path Matters More Than a Smaller Transistor
Huawei states that LogicFolding can reduce the average length of certain interconnects by around 20 percent, while critical paths can be shortened by as much as 70 percent. The company also reports significant reductions in power consumption in certain CPU, GPU, and NPU blocks at the same target computing performance. For now, these figures should be treated as results and estimates presented by the manufacturer itself, but the physical logic of shortening interconnects is not in dispute.
A metal interconnect has resistance and parasitic capacitance. The longer it is, the greater the delay and the energy required to change its electrical state. That is why Huawei calls its new philosophy τ Scaling: the goal is not only to optimize the number of transistors per square millimeter, but also the time required for information to move through the entire system.
Perhaps it can be stated more simply:
When you can no longer easily shrink the transistor, you can shrink the world through which its signal has to travel.
AMD 3D V-Cache — A Familiar Idea, but a Different Ambition
At first glance, LogicFolding inevitably brings AMD’s 3D V-Cache to mind, and the comparison is not unfounded. AMD demonstrated that it is possible to place an additional SRAM layer directly on top of a processor chiplet and, through extremely dense hybrid bonding, dramatically increase cache capacity without increasing the surface area of the CPU layer itself.
But there is an important difference. With 3D V-Cache, the basic idea is to add extra cache memory to an already existing processor chiplet, whereas in LogicFolding the vertical partition appears to be part of the organization of the SoC itself. Compute units and their memory structures are designed to function across both levels. That means the number of inter-layer connections is much greater, and their role is considerably more complex than simply “adding more cache.”
AMD showed how much the third dimension can help the memory hierarchy. Huawei is trying to make the third dimension part of the organization of the processor itself.
Two IPCs We Must Not Confuse
There is an interesting play on acronyms here. In processor microarchitecture, IPC means Instructions Per Cycle — the average number of instructions a processor can execute during one clock cycle. If LogicFolding reduces cache-access latency, shortens data stalls, and improves the utilization of execution units, it can indirectly contribute to improving this IPC.
But in our previous article about HarmonyOS, we used the same acronym for something completely different: Inter-Process Communication, or communication between processes. For a microkernel, this second form of IPC is extremely important, because services communicate with one another through message passing much more extensively than they do in a classic monolithic kernel.
This brings us to an interesting, but still unproven, possibility. Faster cache, lower memory latency, a more efficient scheduler, and quicker transitions between software components can certainly help inter-process communication. However, we cannot conclude from the LogicFolding architecture itself that one of its goals was the direct hardware acceleration of HarmonyOS microkernel IPC.
That would be too confident a claim.
But there is a good reason to ask the question.
When the Same Manufacturer Designs Both the Silicon and the Operating System
Huawei is in a rather unusual position because it simultaneously designs Kirin processors, develops HarmonyOS, ArkCompiler, and its own runtime, while also building Pangu AI models and the infrastructure intended to connect all these layers into a single ecosystem.
The company does not present its τ Scaling philosophy merely as a new method of stacking silicon, but as an attempt at coordinated optimization across devices, circuits, chips, system architecture, and software.
That raises a question for me which, for now, remains more of an engineering intuition than a confirmed fact: to what extent is the LogicFolding microarchitecture designed with the specific characteristics of HarmonyOS, its microkernel, compiler, and runtime in mind?
If you know the operating system, the compiler, and the hardware on which they will run, you gain opportunities for optimization that a processor manufacturer targeting dozens of different platforms does not have to the same degree.
Apple has already shown how powerful such a vertically integrated approach can be. Huawei is now attempting something similar, but under very different technological circumstances.
Forced Innovation
In the previous article about HarmonyOS, we wrote that constraints do not guarantee innovation, but they very often force it. The Kirin 9050 Pro may be an even better example of that statement.
If Huawei had unrestricted access to the most advanced EUV processes, the simplest development path would probably be to build a new Kirin on a smaller process node, increase transistor density, raise performance, and continue along the familiar route.
But that path is not currently open.
So the question becomes different: how do you build a faster and more energy-efficient processor if you cannot shrink transistors at the same pace as your competitors?
LogicFolding is one answer. Not a perfect answer, not proof that geometric scaling has lost its meaning, and certainly not a magical solution that erases the advantages of more advanced lithography. But it is an attempt to change the geometry of the problem itself.
Instead of continuing to expand the whole city across a flat plain, we begin to build upward.
Microelectronics Enters the Third Dimension
Perhaps this is the point where the story stops being only about Huawei. The semiconductor industry has already been moving for years toward chiplets, 2.5D packaging, hybrid bonding, advanced memory systems, and true 3D integration. The reason is not geopolitics alone. Classical scaling is becoming physically more difficult and economically more expensive for every manufacturer.
Huawei, however, because of its own limitations, has found itself under pressure to move in that direction perhaps faster and more aggressively than it otherwise would have had to.
That is why the Kirin 9050 Pro is interesting even if it never becomes the fastest mobile processor on the market.
Its significance may not lie in how many points it earns in a benchmark.
The more interesting question is whether it points toward one of the paths processors may have to follow when the flat surface of silicon is no longer enough.
In the previous article, we saw how Huawei, under pressure, began building its own software world. With LogicFolding, it is trying something similar in silicon.
HarmonyOS attempted to extend the computer beyond the boundaries of a single device, while Kirin is trying to extend the processor beyond the boundaries of a single plane.
Perhaps the most interesting part of Huawei’s experiment lies precisely at the intersection of those two ideas.
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